1. Field of the Invention
The present invention relates to a method of producing a MIS structure such as a silicon gate MIS field-effect transistor.
2. Description of the Prior Art
In general, in an MIS field-effect transistor having an insulated gate portion, the insulating film of the gate is formed to be extremely thin, approximately 1,000 A, because of required characteristics. Moreover, the gate capacitance is several pF or less and is extremely small. Therefore, the gate is sometimes destroyed even by, for example, slight static electricity which is undesirably impressed during handling. There has hitherto been known a method in which, in order to avoid such destruction of the gate, a protective diode, adapted to break down by voltages above a predetermined threshold, is connected between the gate and the substrate of the transistor or between a resistance incorporated in series with the gate and the substrate, thus preventing any voltage above a gate-destroying voltage from being applied to the gate portion.
Similar gate destruction may also occur in a silicon gate MIS transistor which uses polycrystalline silicon for its gate. It is, accordingly, more desirable that the diode also be used in the silicon gate MIS transistor so as to prevent any abnormal voltage from being applied to the gate. Even with the protective method, however, the destruction of the gates has often occured in silicon gate MIS transistors. In order to clarify the cause, the inventors performed a test in which elements where are likely to cause gate destruction were particularly selected by the use of the voltage screening method. "The voltage screening method" is a procedure which is carried out before the final test and in which an MIS-LSI is operated for 5 minutes with its operating voltage held higher by 20 percent. As a result, it was effectively ensured that the gate destruction would be generated at a marginal part of the silicon gate. Upon study of the defects, it was determined that the defects are associated with the method by which the silicon gate MIS transistors are produced. Upon further study, the cause of the defects was inferred as explained below.
A silicon gate MIS transistor employs the so-called self-alignment construction by which an oxide film is first formed on a semiconductor substrate, a silicon layer is formed on the oxide film, the gate portion is selectively formed in the silicon layer, the oxide film is selectively etched using the silicon layer as a mask, and impurities are introduced into the surface of the semiconductor substrate using the gate portion as a mask and in order to form the source and drain. In this case, however, the side face of the oxide film 3a is side-etched as shown in FIG. 3 of the drawings during the etching of the gate oxide film, so that the marginal portion of the polycrystalline silicon layer 4a protrudes in the form of an acute-angled "pent roof" 4c. Such pent roof 4c sometimes hangs down onto the side of the source or drain 6 at a part of its marginal portion. In addition, during the deposition and formation of the oxide film 7, shortcomings such as dirt are liable to gather in the insulator layer 3a under the pent roof. As a consequence, a concentration of the electric field takes place at this part.
Then, a countermeasure has been taken with a method in which the surface portion of the polycrystalline silicon was lightly oxidized to make the pent roof 4c small. Even with such a method, however, the generation of some voltage screening defects was still unavoidable.
The present invention is provided to prevent the gate destruction in such way that the foregoing pent roof portion of the polycrystalline silicon is perfectly removed by etching.